//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
#ifndef _gpio_h
#define _gpio_h

#define GPIO_PIN_IN  0
#define GPIO_PIN_OUT 1

#define GPIO_LOW     0
#define GPIO_HIGH    1

#define GPIO_AS_GPIO 0
#define GPIO_AS_AF1  1
#define GPIO_AS_AF2  2
#define GPIO_AS_AF3  3

#define ENABLE_EDGE  0
#define DISABLE_EDGE 1

#define GPIO_EDGE    1
#define GPIO_NOEDGE  0

#define GPDR0 0X40E0000C
#define GPDR1 0X40E00010
#define GPDR2 0X40E00014
#define GPDR3 0X40E0010C
#define GPSR0 0X40E00018
#define GPSR1 0X40E0001C
#define GPSR2 0X40E00020
#define GPSR3 0X40E00118
#define GPCR0 0X40E00024
#define GPCR1 0X40E00028
#define GPCR2 0X40E0002C
#define GPCR3 0X40E00124
#define GRER0 0X40E00030
#define GRER1 0X40E00034
#define GRER2 0X40E00038
#define GRER3 0X40E00130
#define GFER0 0X40E0003C
#define GFER1 0X40E00040
#define GFER2 0X40E00044
#define GFER3 0X40E0013C
#define GAFR0_L     0x40E00054      //GPIO alternate funciton select register 15:0
#define GAFR0_H     0x40E00058      //GPIO alternate function select register 31:16
#define GAFR1_L     0x40E0005C      //GPIO alternate function select register 47:32
#define GAFR1_H     0x40E00060      //GPIO alternate function select register 63:48
#define GAFR2_L     0x40E00064      //GPIO alternate function select register 79:64
#define GAFR2_H     0x40E00068      //GPIO alternate function select register 80
#define GAFR3_L     0x40E0006C      //GPIO alternate function select register 79:64
#define GAFR3_H     0x40E00070      //GPIO alternate function select register 80
#define GPLR0       0x40E00000      //GPIO pin-level register 31:0
#define GPLR1       0x40E00004      //GPIO pin-level register 63:32
#define GPLR2       0x40E00008      //GPIO pin-level register 80:64
#define GPLR3       0X40E00100
#define GEDR0       0x40E00048      //GPIO edge detect status register 31:0
#define GEDR1       0x40E0004C      //GPIO edge detect status register 63:32
#define GEDR2       0x40E00050      //GPIO edge detect status register 80:64
#define GEDR3       0X40E00148

void xs_setgpio_dir(int gpio_num, int direction);
void xs_setgpio_outhigh(int gpio_num);
void xs_setgpio_outlow(int gpio_num);
void xs_setgpio_RER(int gpio_num, int isedge);
void xs_setgpio_FER(int gpio_num, int isedge);
void xs_setgpio_AFR(int gpio_num, int function);
void xs_clrgpio_EDR(int gpio_num);

int xs_getgpio_inLEV(int gpio_num);
int xs_getgpio_EDR(int gpio_num);

#endif // _gpio_h
